Hi Dario, When I first joined tomorrow the Akademi, I noticed that all the resources were already available. I thought this was a special gift for us for the opening, and I was really thrilled! Thank you so much for your generous gifts. 😊 Now I can access all the modules, and I just hope they won’t be “closed for renovation” anytime soon 😄. Best regards,

Thanks for the clarification, Dario! 😉 Now I understand why I felt like I was in a “parallel universe” 😄. I’ll make sure to switch communities and explore the new ones!

Hello everyone, I apologize for commenting a bit late, as I have just joined the group. I recently finished the Power Delivery Networks course, and like  Ivan Mendez alonso, I find some parts quite confusing. So far, I have mostly selected decoupling capacitors based on reference designs. However, I learned in the course that this approach is not always correct; capacitor values should be calculated properly and ideally be the same. I’m particularly struggling with the calculation part.To determine the target impedance, I need to consider the transient current. I tried using the formula: I transitent= n*Cpd*Vcc/Tr The datasheet only specifies Pin Capacitance = 2 pF, and I could not find information about tr. Therefore, I could not calculate the target impedance. Also, the 2 A value used in Ivan Mendez alonso example seems quite high to me, and I’m not sure where this value should come from. Using approximate values, my calculations indicate that theoretically, a very large number of capacitors would be required. However, placing so many capacitors would significantly lengthen the routing and negatively impact ESL. My question is: How can I translate this theoretical capacitor calculation into a practical PCB design? In other words, theory suggests a large number of capacitors, but how can we manage placement and routing lengths in practice? I would greatly appreciate any advice or experiences you can share. Thank you in advance.

Sorry Dario, I am level 2 so i could not open a new task :(

Even though this conversation is a bit old, I’m new to the group and very interested in this topic because I also use these components and separate AGND and PGND on my PCBs — just like Nazar 😊 Normally, I design the PCB according to the datasheet, and yes, some datasheets recommend separating the ground regions. However, I’m a bit confused: when I design 4-layer or higher stack boards, I never separate the return plane (GND). But if I’m working on a 2-layer PCB and the datasheet explicitly suggests separating the grounds — should we still insist on keeping a solid return plane, or follow the datasheet recommendation? From my experience, keeping a solid return plane on 4-layer designs significantly improves EMI and signal integrity, but in 2-layer layouts it becomes more challenging to manage switching and analog return paths. Even though we know that 2-layer PCBs are not ideal for switching converters, sometimes we still need to design them due to cost or mechanical constraints.

Thanks a lot for your insights, Dario! I really appreciate your perspective and advice.