Decoupling capacitores Values
I have read in many CMOS IC datasheets that the typical values for decoupling capacitors are 100 nF, but on the other hand I have read an article by Eric Bogatin stating that this is a false myth and that this has been going on since the 80's when CMOS IC voltages were much lower. Actually he refers to calculate the decoupling capacitors with respect to the CMOS frequency and their rise times. Could someone clarify me which is the correct way of sizing the decoupling capacitors and the technical reasoning why? I would like to clear this doubt and when I search the internet I see disparity of opinions. thanks.
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Ivan Mendez alonso
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Decoupling capacitores Values
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