Good Morning All!
Just wanted to have a discussion based on Phase 9 of the IEC 61511 lifecycle; ‘Verification’. I often see this phase been overlooked and only ever hear the word ‘Verification’ associated with SIL Calcs.
Within the standard it specifies that at the end of each lifecycle phase, there should be a Verification check done to ensure the required outputs satisfy the defined requirements for the appropriate phases as identified by the verification plan.
I think a good project FSMP should include a Verification Plan, but I often see this section being missed from most.
I guess my question here is what experience does everyone here have with Phase Verification, and how do you normally implement it throughout a project?